That's really interesting, I am not familiar with the ztex projects (they don't compile in my preferred synthesis tool, synplify pro). I would not have expected it to run on the V6 with that usage @ 300 MHz without additional pipelining. Maybe I'll take a look at that project and see what the big difference is.
I used the old veriliog port to get to 300 MHz on mine (adding DSPs and pipelining), but the power usage is around 7W due to the use of the DSPs.
Thanks for you hint. I've already tried SmartXplorer with default 7 built-in strategies, but can't achieve above 160MHz result. so, you mean I should use the cost table method to brute force it? thanks.
Yup. For reference, the released bitstreams took days/weeks to compile.
xbaby,
You can also try to floorplan the DSP48s if you want to cut your runtime. To get the boards I have with V6 130Ts to run at 300 MHz, I had to constrain each of the DSP48s, otherwise there was no chance. This was based on the original verilog port, but I'm sure the problem with no pre-placement is the same.
Hi, thanks for your tips. I'm compiling the "X6000_ztex_comm4" project, which doesn't use any DSP48 block as I know. I also successfully compiled the same project on V6 130T device (with minor fix for MMCM, FIFO, JTAG core), just achieve at most 300MHz, same as yours, but no DSP48s. the compile time of V6 device is much less than spartan6 LX150. I guess the long-route resources of virtex6 make the difference.
next, I want to try difference implement options to go higher target, such as 350MHz.
BTW the power estimation given by ISE of V6 130T @ 300MHz is about 10W. below is the resource usage:
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 85,173 out of 160,000 53%
Number used as Flip Flops: 85,172
Number used as Latches: 1
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 57,385 out of 80,000 71%
Number used as logic: 34,910 out of 80,000 43%
Number using O6 output only: 14,978
Number using O5 output only: 539
Number using O5 and O6: 19,393
Number used as ROM: 0
Number used as Memory: 9,759 out of 27,840 35%
Number used as Dual Port RAM: 0
Number used as Single Port RAM: 0
Number used as Shift Register: 9,759
Number using O6 output only: 9,759
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 12,716
Number with same-slice register load: 12,452
Number with same-slice carry load: 264
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 15,859 out of 20,000 79%
Number of LUT Flip Flop pairs used: 62,383
Number with an unused Flip Flop: 1,382 out of 62,383 2%
Number with an unused LUT: 4,998 out of 62,383 8%
Number of fully used LUT-FF pairs: 56,003 out of 62,383 89%
Number of slice register sites lost
to control set restrictions: 0 out of 160,000 0%