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Topic
Board Hardware
Re: Official Open Source FPGA Bitcoin Miner (Last Update: April 14th, 2013)
by
iidx
on 10/05/2013, 05:38:42 UTC
Possibly, but I used some compiler directives to force SRLs and registers in certain situations so the design would fit.  In XST it infers too many of register or SRL to properly fit, so some manual instantiation might be required.

I'm still surprised that the Ztex project would hit 300 Mhz without extra pipeline stages.  I think that it might be better to add DSPs to that project instead?