Quote from: MrTeal on June 08, 2013, 05:29:26 AM

Quote from: GalaxyASIC on June 08, 2013, 05:23:13 AM

Quote from: bitfury on June 08, 2013, 04:30:46 AM

Quote from: GalaxyASIC on June 08, 2013, 04:20:51 AM

How many cores are in the chip and how many clock cycles does it take to get a result?
Does each core has GPIO or is there some serial but that aggregates them?
Does your QFN48 7x7mm packaging has exposed thermal pad and is it on top or bottom?

1. 756 double sha256 cores. 61+4 kernel (61 clock cycle computation 4 clock cycle load).

2. There's asynchronous 'match' signal - the only thing that core sends out. And some busses to load data.

3. wirebond. die is laid normally in cavity. i.e. it is not flip-chip and not arranged to give heat into anything else, but PCB.
It is actually not complex to dissipate 3W... Maybe even 5W with metal-core PCB and proper cooling. That's what we'll see.

756 double cores in 7x7mm package?, how many gates approximately in each double core and what are the die dimensions?

You should probably read a little on the design philosophy bitfury used in his previous FPGA design. I believe he fit 82 cores in an LX150.

die dimensions - 3.8x3.8 mm
160x99um approx. kernel size (that's two sha256).
dimensions are as in die (scaled down to 55nm from 65nm).

Gates - I cannot say easily that's full-custom design and can't extract that count easily. NAND2 approximation would be 4, but my cells are actually more complex.
Number of non-cap transistors found from cell kern32: 54558

And... there's still some things can be done better, but more risky - it's kind conservative design as I am doing this first time in my life and want to have as best success chances as I may get.
So it can be done better - but that's I think is what I'll do for smaller tech nodes. Also... 15% of die went to auxiliary circuits such as padframe, ESD, some control, etc.