Quote from: jimmy3dita on June 10, 2013, 10:46:45 PM

Anyone knows if the Avalon chips project is a sort of "hard copy" of the Icarus FPGA? It can explain why it has a structure like that (from the little that I know, the FPGAs are basically the same, just bigger and programmable).

No, it's not a "hard copy" of FPGA. It might be based on the similar algorithm implementation, but that's the extent of similarities.

Quote from: jimmy3dita on June 10, 2013, 10:46:45 PM

By the way it's probable that you can't go lower than 110nm production process if you want to keep temperatures under control and maintain the QFN package. That's why BFL had to redesign the chip and use the FCBGA package, with that shiny upper surface (very vulnerable too, they have something of the old AMD Athlon Palomino CPUs).

That is not exactly true. In CMOS you can always lower power consumption by an order of magnitude by lowering supply voltage & clock, and then compensate for that by using more chips (power drops non-linearly, so there is a benefit).

Quote from: jimmy3dita on June 10, 2013, 10:46:45 PM

Borrowing information from other products (i.e. systems on a chip like the ARM Cortex) 28nm is often a "die shrink" of an existing 32nm chip, so if Orsoc/KNC has already been able to make a 32nm chip it's not hard to think that the first prototypes will use this bigger (and less efficient) die, doing the shrink when everything is -almost- fine. It "should be" better, I still remember what happened when Intel launched the P4 Prescott series...

You cannot simply shrink the die on the modern processes as it was possible at the times of 350-800nm technologies. You must redo almost everything - there is just way too much constraints, and too much changes with this "mere" 14% shrink.

Quote from: jimmy3dita on June 10, 2013, 10:46:45 PM

I forgot to mention that the BFL chip is made by Global Foundries with a production process of 65nm.

Any links on who to ask to get a sample chip from them?