Quote from: greaterninja on June 21, 2013, 09:57:29 PM

Congratulations Bitfury!

I should be #6 on the waiting list ; please send samples to me so I can tinker with them

I think I said this before, but I work for the #2 supplier of chip packaging solutions in the world. I have a Russian translator, and 1-2 Electrical Engineers on hand to help find improvements.

I can probably find resources to help get this thing going faster.

The current chips are in 7x7 QFN48 package and the die is 3.78x3.78. We are trying to find ways to reduce the inductance on (length of) the package bonds and going to a 6x6 package is an option. Another option would be to create a multi chip package or a chip scale package that would add more capacitance closer to the die. Your ideas on that would be welcome.

We will compile a list of tester early next week.