Quote from: intron on June 24, 2013, 10:07:39 PM

Quote from: bitfury on June 24, 2013, 08:49:19 PM

Quote from: intron on June 24, 2013, 08:38:45 PM

Normally, IOREF is set with a restistor divider to half
IOVDD (normally 1V8). To make the board simpler, IOREF
was connected to core voltage.

http://imgur.com/QZYoGDQ

Core voltage was adjusted between 0V59 and 0V83 V and operation
of the chips remained normal.

Leszek/bitfury, can this be done on the miner board also?
Reduces the wiring a bit.

intron

Yes. This is why IOREF pin is there (near VDD

. If you don't use external clock and spi is slow enough (you don not worry about width distortion) - it will work just perfectly. But when you slice CMOS signals not exactly at 50% level - then - you would encounter slight width distortion caused by sampling differences.

So what to do on the mining board: connect IOREF to Vcore or connect IOREF to IOVDD/2?

intron

VDD => lets's forget the IOREF line.