Quote from: BkkCoins on July 08, 2013, 01:39:32 AM

Quote from: chaoztc on July 08, 2013, 01:20:12 AM

the dead-zone could be avoided if the nonce is read from the sram and then rearm the sram.
only after this send the next hash to the asic.
(and not much "time" is lot as not every hash gives a nonce?)

I will give it a try (already ordered the part)

Just realized the CS line probably needs to be used as well, though maybe it can be somehow merged with OE.

I'm not sure a dead zone after each nonce is a problem anyway as the chances of two nonces being sequentially close is quite low. The probability is likely low enough that losing the second nonce would have no noticeable effect on overall performance.

However, if the work units are fast (16 chips is pretty fast, 0.9 secs), then the delay of waiting for new work to grab nonces isn't long. The SRAM can capture all the nonces sequentially for a work unit. Then just before pushing new work we read the SRAM and push new work. That way the deadzone happens during duplicate nonce time which are ignored anyway. So the tick counter would trigger nonce read and then work push. The nonces can be read until a zero word is read, and then rewritten with zeros, and armed for write.

Sigh, this is (sort of) what the Icarus bitstream does also - if 2 nonces arrive at the same time, you lose one.
The only catch of course is that "at the same time" can be a long time frame with regards to hashing nonces ... which increases how often it happens.
Hopefully here "at the same time" is a VERY small window.