Quote from: gill83 on July 10, 2013, 08:31:52 AM

Dear BkkCoins,

Can you please elaborate a little about the changes that you made to the circuit, to make it work? I know about the missing power to the PIC, and the little jumper cable that you soldered to power it. What is that small red PCB doing? I also got a sample board made around the time you did. I also got 2 sample chips that I have mounted. But for some reason the board is not hashing.

The red board has 2 NOR gates wired as I described a few posts back up above.

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I use a trailing edge delay circuit. The first NOR gate has P and N, and it's output goes to A of 2nd NOR gate, then through a 100R resistor to B of 2nd gate. B has the 30pF to GND. So the 2nd NOR is ORing the clock with a delayed clock. The UART is set for rising edge capture, and data is inverted when read out of FIFO (~RCREG). This will be updated in the schematic very soon.

The reason it's on a second board is that I had changed the parts so many times on the main board that the PCB traces lifted off. I tried at first to wire the 2nd NOR gate in dead bug style next to the first, but the legs on that tiny gate are too delicate for me and kept coming off. I think I wasted about 4 or 5 over the time I did all that. Once I dug out that board and soldered it down it was easy to connect wires and hook it to the sides of the pullup resistors on main board. The NOR gate on main board was removed because it's output pad had lifted and leg broke off.

Make sure you placed the first ASIC at either location U6 or U9. If U9 then you may need to alter the source code slightly from what I posted since I'm testing on U6. The chips are daisy chained so if you mount one elsewhere then it won't get data.

Even without changing the NOR gate circuit you should get result data, so if you're not then you'd need to start debugging the circuit. I would double check all your QFN pins and make sure none are shorted. Check power is correct for all 3 supply outputs. For one of my chips I had a short underneath that shutdown the 1.2V supply.

If power looks ok then you'll need a scope probably to go further. You can set a falling edge trigger on one lead and then look at the inputs to U6 while sending work with ktest. You should be able to count the pulses and see brief stretched pulses where the data type changes - clock cfg, merkle, precalc, midstate, precalc, nonces. For one or 2 chips the nonces are easy to see as they will be all zero, except the last bit which rises just slightly before the end. If you have data in that looks correct then start scoping the result pins.

The source code is changing hourly here but I try to post when it's working. I fixed some bugs this morning after rewriting the result rx code. It took forever to figure out why the timing was all off. Turns out some compiler bug causes it to not handle const data correctly. It was pushing garbage into the nonce values. It didn't do that before but when I removed the const keyword from the BankRanges array it started sending correct nonces again.