New scope pr0n... with extra inverters, showing a 1 bit and two 0 bits.
I think this was at 390 MHz. Shows fixed 50nS delay on clock trailing edge on input to PIC. Note this inverts data and clock so now the code is set for falling edge capture and no longer inverts RCREG upon read.
http://i.imgur.com/NmZ6qQN.jpg
I think this was at 390 MHz. Shows fixed 50nS delay on clock trailing edge on input to PIC. Note this inverts data and clock so now the code is set for falling edge capture and no longer inverts RCREG upon read.
http://i.imgur.com/NmZ6qQN.jpg
BKK - That spike in the red line at -50nS (when the yellow goes down 1->0) - is that introduced by possibly too long probes?
If not - that's 0.8V from peak to peak and I'm wondering if it introduces any other issues at higher frequencies ...
My guess is that it could be either due to the red and yellow wires being too close, or most likely sneaking in via the power lines ... maybe some more decoupling capacitors?
That's just an observation. If it doesn't cause any issues please disregard my note and let's stick with the K.I.S.S. principle
edit: there is also that huge spike when it goes from 0 to 3V3 (4.4V peak when just the red switches, or 5V when both switch). Again - if it's not an issue - don't bother fixing it.