Quote from: 2112 on July 26, 2013, 02:05:33 AM

Quote from: eldentyrell on July 26, 2013, 01:41:18 AM

But the biggest problem by far is that parasitic capacitance scales in really funny ways across process nodes an even between fabs.

Also, the parasitic capacitance may not be entirely parasitic. Check out bitfury's post where he describes how he used 1/4 of the chip area to place bypass capacitors close to the sources of the current spikes:

Er, decoupling capacitance (what you describe) doesn't affect power consumption -- at least not anywhere near as much as parasitic capacitance does. Decoupling capacitance smooths out spikes in the supply, but it doesn't increase power consumption (except for leakage).

The industry's been doing this for a while now.. the Alpha 21264 had a crazy 320nF of on-chip decoupling capacitance. I think that was also the one that had two solid sheets (not grids!) of metal for power+ground (EDIT: no, that was the 21164).

Quote from: bitfury on February 07, 2013, 02:19:48 PM

unfortunately 26%-28% of DIE AREA is just capacitors Sad

not transistors... not logic... that's big sacrifice and it won't be stable especially in low voltage without that... capacitors placed near flip-flops;

Ah yes, one of the many downsides of synchronous chips. They're so fragile when it comes to power supplies...