Quote from: HyperMega on July 31, 2013, 08:52:38 AM

Quote from: Anenome5 on July 30, 2013, 11:11:53 PM

Quote from: minternj on July 30, 2013, 11:03:29 PM

Quote from: Anenome5 on July 30, 2013, 10:45:00 PM

But of course, BFL did something so silly where they apparently failed to do optical proximity correction, and this is, apparently, why their power drain doubled.

Are you saying this as a fact? If so please link source.

No, that's why I qualified the statement with 'apparently,' obviously. However it would explain why their power targets are off by an order of magnitude. And it's one of the more charitable explanations other than outright incompetence.

Quote from: minternj on July 30, 2013, 11:03:29 PM

Quote from: Anenome5 on July 30, 2013, 10:45:00 PM

I don't expect Orsoc to pull such a rookie move.

Bitfury also missed original power goals. You saying hes a rookie too?

They're not off by an order of magnitude. It's not quite in the same ballpark therefore, is it.

A: Rookie mistake.

B: Estimate proved optimistic.

Sorry, as somebody who already executed the one or the other 65nm/40nm/28nm tape-out including direct contact to foundries, I like to mention that BFL and its design enablement partner for layout generation/sign off (Chronicle Tech?) were for sure not responsible for the OPC.

OPC is a task of the mask preparation, which is normally done at the mask house related to the foundry before wafer manufacturing can start. The responsibility for this step has the foundry, which was Globalfoundries in case of BFL.

An order of magnitude? Wink

Do you mean 10x? When I remember right, BFL targeted below 1 J/GH and reached 3.2 J/GH. Should be 3.2x.

Anyway, a missed OPC would result in a very bad yield, maybe even in no yield. The influence at power should not be that strong.

From my point of view, the reason for missing the power target, was the design methodology of the BFL ASIC. It's impossible to run detailed accurate power analysis (e.g. for calculation of a complete hash) during design phase for this kind of design sizes, if you do a full-custom design (hand layout). The reason for this is, that these kind of analysis have to be done at transistor level in case of a full-custom design. I doubt that there is a spice simulator, which can simulate a complete pipelined hash core. If there is one, such a power analysis would take weeks.

So I assume, that BFL did power analysis only for small parts of one hash core and than they tried to scale it up (if they did at all). With respect to power consumption they were a kind of blind till late in the implementation phase. I also think that they realized that they have a problem shortly before tape-out. That was the reason why they change the package from a simple wire-bond QFN to a flip-chip BGA late in 2012 to be able to handle the much higher power consumption.

I will defer to your wisdom and knowledge in this topic.

Quote

It's impossible to run detailed accurate power analysis (e.g. for calculation of a complete hash) during design phase for this kind of design sizes, if you do a full-custom design (hand layout).

I have not read anyone else say they attempted a full custom design. Someone mentioned the old proverb 'you must walk before you run,' the hell were they thinking.

They went for a home-run and struck out at the plate.