Quote from: KS on August 02, 2013, 02:13:45 PM

Quote from: HyperMega on August 02, 2013, 02:06:08 PM

Quote from: KS on August 02, 2013, 01:35:16 PM

Quote from: HyperMega on August 02, 2013, 12:49:28 PM

Quote from: KS on August 02, 2013, 12:20:11 PM

Quote from: HyperMega on August 02, 2013, 10:43:22 AM

Quote from: FeedbackLoop on August 02, 2013, 09:44:08 AM

Quote from: HyperMega on August 02, 2013, 08:47:52 AM

I doubt that KnC or OrSOC is seen as a big customer for this project, because they probably will not order more than 50 wafers in the first year (which would be already about 3 PH).

3 PetaHash/s ? That's a very interesting number. Could you expand the calculation for us? If I am seeing correctly that would be 10 times the present total network hashing power.

Is 50 wafers some sort of bulk discount number or some sort of standard order? Maybe there;s some minimum amount of wafers?

Thanks!

KnC ASIC will have about 100 GH/s realised with 192 engine IPs (see KnC R&D news from 7/19/2013).

I assume that an engine IP is equivalent to a pipelined hash core. To realise 100 GH/s they must run at a little bit more than 500 MHz, what is feasible in 28nm.

Based on technology scaling (2x more logic on same area form technology node to next technology node) we get based on BFL hash core size (estimated based on BFL die including 16 cores removing spare area and pad frame overhead) from 65(55)nm -> 45(40)nm -> 32(28)nm an estimated area per hash core of 0.6 mm2 in 28nm.

This results in an overall KnC die area of about 115 mm2 (0.6mm2 x 192).
Adding some area for supporting logic, I would say max 120 mm2 would be a good target.

An 28nm 300mm wafer has an area of about 70000 mm2. So we get 583 dies per wafer (assuming 100% yield, not realistic I know, but you can scale it yourself to your yield assumptions).

For 50 wafer:

583 dies/wafer -> 58.3 TH/wafer
50 wafer -> 2915 TH

Minimum ordering at foundries is normally one lot (25 wafer). Maybe also half lots are possible. But keep in mind, additional wafers costs nothing compared to the initial mask costs.

+3000TH. That sounds very scary for anyone wanting to meet ROI. Anyway...

Would they need a 55mmx55mm package for a 11mmx11mm chip??

They choose the package size to handle thermal and power requirements (ir-drop and so on). It's a flip-chip design with a custom package substrat (to be designed to fit to KnC die). In principle there is no problem to put a 11x11mm2 die flip-chip on a 55x55mm2 package substrat.

Wire-bond would be a different story. It would not be possible to bond a tiny die in a huge package, because the bond wires would get to long. But KnC is NOT doing a wire bond design like e.g. Avalon/ASICMiner or Bitfury.

Thx for pointing out the flip chip/wire-bond difference. How optimistic are you about the die size? Is that fairly accurate or "fingers on screen" accurate? Wink

120 mm2 in 28nm is really really huge, but can be produced. Approximately 4 dies per reticle. A nightmare were for sure the toplevel layout implementation and power sign-off.

They will have for sure yield issues, but if they integrated suitable redundancy features it should be handleable.

With respect to design complexity the related BIST (built and self test) and redundancy logic, will be as complex as the pure miner logic Wink

. I hope they verified that right, because this was probably not part of their FPGA prototype.

EDITED: To your original question. I'm pretty sure, that if the KNC die is bigger than 120 mm2 they did not a good layout implementation job. This is the minimum target that they must reach to take full advantage of 28nm (better smaller).

Aren't they already in problem land wrt the heat issue for such a small die? Won't having it smaller be worse actually? (wrt heat dissipation)

In principle you are right, but why waste all this expensive 28nm area? If you want to take full advantage of the technology scaling, you have to get as small as possible to be cost competitive. Otherwise you could also go for a 40nm implementation which would have half of the NRE costs of 28nm.

Forgot to mention, the nice effect is that power consumption scales with area, because you will have on-die shorter wires to connect the logic cells, which means less capacitance load in case of switching.