Quote from: 2112 on August 03, 2013, 01:58:09 PM

Quote from: HyperMega on August 03, 2013, 09:27:05 AM

I don't say, that such an implementation is impossible. But it's is extremely risky and the thermal and power issue will be the hell. And based on what they have shown so far, I would say they are far away from tape-out.

Thermal and power and simultaneous switching noise. Standard cell libraries are designed for standard toggle rates. SHA-2 is very close to the theoretical maximum toggle probability (when doing the approximate/probabilistic power/thermal/noise simulations).

Is there any evidence that Uniquify designed a IC that required a heatsink? Or are they experienced CAD-monkeys that "design" ICs by cutting and pasting "intellectual property" black boxes to create SoC-s for the portable and battery-operated market segments?

It would also probably help to define what the word "risk" means here. It isn't the risk of getting a non-working or extremaly bad yielding chip. The risk is that the chip has to be severely derated to actually work. And by derated I mean underclock but overvolt to combat the internal noise in the chip.

The helveticoin user was also from some established ASIC design house and they had 28nm prototype hashing chips either late last year or early this year. But their design seems to be non-viable commercially because it was designed like just another integrated peripheral for the SoC CPU.

Oh, I see, you know what you are talking about!

But I think there is also a higher risk to fail completely at the first time, because the expected extreme power noise will have effect on setup and hold timing. If they miss hold violations caused by power noise, they can't solve these issue by just reducing the clock frequency or changing the supply voltage.
Ok, if you search long enough you will maybe find a sweet point, where the ASIC runs stable without errors, but this point could be individual for each single die in worst case.