Quote from: tucenaber on August 04, 2013, 04:16:59 PM

Quote from: labcoin on July 05, 2013, 11:57:48 PM

Today we have a very important update, the Chinese team is simulating a lot of design simultaneously and worked almost non-stop for the last 48 hours targeting different process sizes.

The results are more than positive, i will try to outline them in the clearest way possible.

1) The 65nm 500Mhz is still undergoing post-verification phase, while another simulation is ongoing at 600Mhz and we're waiting for the results.

2) Post simulations yielded positive results on a 130nm, 300Mhz, Power 0.8W, 6.5x6.5mm design.

   The team is working on HDL optimizations to get 16 cores for chip.

   Some math, quoted from the tech team

Quote

"300M*16=4.8G, 0.8*16=12.8W, Area=130,0000*16=2080,0000, make the utilization ratio to 50%, the chip size will be about 4160,0000um2, about 6.5mm x 6.5mm"

"Power consumption per GHash is 12.8W/4.8G=2.7W/GHash"

"Estimated selling price for chip, 8-9 USD"

What does this mean ? i think it's not hard to get. 130nm process and 5GH speed at slightly higher power consumption, but competitive prices.

Shoot any question guys

Sam
Labcoin team

How can this version be so much smaller than the earlier 180nm design? I assume this is more or less the 180nm chip design shrunk to 130nm, and the numbers seem right except for the size. How in the world can you fit 16 cores in that small area? I can't make sense of it. The 180nm version would be 5mmx5mm so this one should be a square with 5mm*130/180=3.6mm, no? 16 of these would be 14x14. Can anybody help me figure this out?

+1

It's called "designing IC's by multiplication"! Where are the proper simulation results?