Quote from: Minor Miner on August 06, 2013, 06:32:33 PM

Quote from: HyperMega on August 06, 2013, 06:27:06 PM

You probably know that most of their NRE costs are 3rd party costs, which they have to pay before they will have any ASICs in their hands.
Correct me if I'm wrong, but they can only refund customers with money they still have, can't they?

HyperMega;
You know any 28NM foundries that let you book space or will even give you a QUOTE on a wafer run before you design is complete and submitted to them? Any idea on the advance notice you need right now to get a 28nm lot done? Money in June to get through vetting process, then they would sign an NDA and start designing, then submittal, then quote, then booking, then wafers, then chips, then..........How many days between June 15 and end of September (math was never my thing)?
This could be a record.

Smaller companies like KnC or OrSoC normally do not deal with foundries like GF or TSMC directly.
When they want to realize an ASIC they have to contact an agreed channel partner of such a foundry. These partners are also resellers of the technologies of the foundries and they can make you a quote.

A finalized design (chip layout) is no prerequisite for a quote. You only have to have an idea of your target technology (including the technology flavour e.g. LP or HP), the final die size and the required tech options (e.g. metal stack). Then the channel partner can make you a quote.

KnC/OrSoC did an RTL hand-off. This means that there has to be an additional partner for the ASIC synthesis, layout implementation and sign-off. In ideal case this partner is also the channel partner, because then he has most likely already done tape-outs with the concrete 28nm technology, has all the physical IP (standard cell libraries, PLL, IO cells) in place and knows how to use them to realize an energy efficient/high yield design (which is not trivial in 28nm for a huge die > 100 mm2).

They said that they selected the foundry (probably through a channel partner) mid of June. The layout implementation was most likely not started earlier, because you can not manufacture a design implemented for TSMC at GF and vica versa. Their 28nm technologies are not compatible at the layout level. Channels partners normally do not make you a layout just for fun. Wink

It is true, that an ASIC miner design is simple from the functional point of view (RTL). Two master students can design, verify and bring it to an FPGA evaluation platform within 3 weeks.
A 28nm layout implementation of it is not that easy. One reason for that is the resulting extreme power density (>10 W per 10 mm2 silicon area). One would need an implementation team, which knows how to realize such high performance designs. I guess there are not many of such teams worldwide. I would estimate 8 weeks for such a task, if you want to do it carefully.
Maybe one can do it in 6 weeks. If you do it "fast&dirty" also 4 weeks maybe possible, but that would be a real challenge.

Lets assume they did it in 4 weeks. Then tape-out was mid of July. If they get high priority at the foundry ("rocket run") then the pure initial mask generation and wafer lot manufacturing would take 45 days in absolute best case.
The package is complex. The 300 mm wafer must be probably bumped at another facility (additional partner), before they can be diced in dies and put flip-chip to the package substrate. I would estimate that this will take about 1 to 2 weeks minimum for the first samples.

So where are we:
Tape-Out -> 15th July
Wafer Fab-Out -> 31th August
Packaged samples for lab characterisation in KnC hands -> 15th September

Again, this is an absolute best case plan. Everything must run perfect for it.

How long it takes to bring the ASICs to an PCB, debug all the related firmware and FPGA design on the linux daughter card, to have finally a working miner they can send to customers you can estimate yourself. But 2 weeks are not much time for that tasks. Wink