Quote from: Ytterbium on August 16, 2013, 09:34:50 AM

Quote from: kingcoin on August 16, 2013, 05:45:57 AM

Quote from: Ytterbium on August 16, 2013, 02:11:01 AM

Quote from: titomane on August 15, 2013, 10:09:54 PM

Do not be angry, but it seems that these guys do not know what they make.
If you have a chip with 192 cores asics performing a hash per cycle.
520,000,000 cycles are 520 Mhz 99840000000 hashes 99.84Ghs
620,000,000 cycles are 600 Mhz 115200000000 hashes 115.2Ghs

But this is not important, the important thing is to know ETA chips.

You're right. It's not important.

But other then that of course they don't know what the final specs will be. They won't know that until the chips are done. It depends on the yield as far as the hasher engines. It depends on thermal output. It depends on a lot of things. Avalon chips are actually underclocked and undervolted, presumably to help with cooling and power, yet they perform 36-40% better then what they were advertized as. . That's because Bitsyncom gave themselves a large margin between what they advertized and what they were designing for (their chips work up to 450Mhz at the right voltage)

Actually you do know the performance of the chip before it's made.

The ASIC vendor will give you timing models and you run static timing analysis on your design and it will tell you the critical path and how fast the device will operate.

However, in most cases the produced device will be faster than the spec. Hence it's possible to overclock the device. But you have no guarantee that the next batch of devices will be as fast, it might be slower, or it might be even faster.

As for thermal they should have a pretty good idea. You try to run a worst case simulation where you generate a VCD file which will show how all the nets in the chip is toggling. Then you run this through some power estimation tool (given a specific package) given by the vendor. This is not 100% accurate and depends on how representative the VCD file is for your worst case. But it gives you a pretty good estimate. Then there are tools to simulate the thermal characteristics of your mechanical system.

BFL was way off, and Bitfury's chips also ended up using more power then expected. And, of course if the power draw is too high, then you have to do things like reduce the clock speed/voltage in order to keep it cool. It's reasonable to give yourself some design margin since other bitcoin ASICs have used more power then anticipated.

So, I'm sure they have an expected value, but they won't know if their simulations are correct until the chips arrive, and if you say "our chip uses x Watts" and design the system around that, and you're wrong, then you're fucked (that's what happened to BFL, all their fans/PSUs didn't work)

That is true. The timing models and static timing analysis of the ASIC's are very accurate. But they are given at a certain power supply level and temperature. If you mess up your mechanical, thermal and PSU design so these conditions are not satisfied then you're pretty much screwed.

However, if you then start to test your system and push the margins you will be screwed again since you don't know where in the process window the particular chip you have in the lab is. If it's a best case device then your systems might fail when you get a new batch of ASIC's which are not best case. Your production line will halt and you have to start debugging again. Or even worse, if your production test is not optimal you will not notice until customers starts to complain and return your product.