Quote from: HyperMega on August 16, 2013, 12:27:04 PM

Quote from: kingcoin on August 16, 2013, 11:27:25 AM

That is true. The timing models and static timing analysis of the ASIC's are very accurate. But they are given at a certain power supply level and temperature. If you mess up your mechanical, thermal and PSU design so these conditions are not satisfied then you're pretty much screwed.

However, if you then start to test your system and push the margins you will be screwed again since you don't know where in the process window the particular chip you have in the lab is. If it's a best case device then your systems might fail when you get a new batch of ASIC's which are not best case. Your production line will halt and you have to start debugging again. Or even worse, if your production test is not optimal you will not notice until customers starts to complain and return your product.

There will be for sure a lot of fun in the KnC lab! Wink

They stated at the open day, that they will not do any classical ASIC production tests (neither wafer test nor final test). If this is still true, it means they will package the dies and put the resulting chips on the PCBs blind.
If the chips work at all and at which speed they probably can determine by running a complete miner only. In worst case this can result in tweaking each box individually.

That's insane. If something is wrong they will not know if it's a problem with the ASIC or not. They can't complain to the ASIC vendor either and they will not have a clue in terms of yield. Did they do this to save time so they would not have to learn and run ATPG tools?