I was looking at the PCB for the K16 and noticed that the PLL ground is connected directly to digital ground under the Avalon chip.
Does anyone know if this I how the Avalon reference design connects the grounds together?
The PLL ground lead on the ASIC is lead 8.
There is no problem with this. Zero-Potential should be the same on the whole chip to prevent leakage currents.
The only possible problem is that the digital ground is noisy and by connecting the this that way maybe the noise would get into the PLL circuit and cause problems. I was wondering if anyone knows where the PLL ground gets connected in the reference design. If the reference design connects the ground the same way as the K16 then I would not worry about it.