Damn, that's just about the worst case. There are only two means of accessing this FPGA:
- Ethernet (not exactly trivial on the FPGA side, but in theory this board could mine standalone!)
- A built-in USB blaster (USB to JTAG bridge), which cannot easily be accessed from anything else than the Altera tools.
Hm, there is a FPGA communication package that 'speaks' UDP on opencores that could be used. Of course the can be some packets missing, since UDP has no provision for package loss ( i would use a sequence number an send a nonce multiple times ...
The other was would be the jtag solution, there is an advance debug system on opencores that uses jtag, as far i understand the docs, it does not require Altera software, but i think it needs some more effort to get it running. I did not dug into, as i am a fan of the serial solution but on the other hand, i still looking for transfering the jtag-communication to an arm system so i could power off my PC at night (given there are no compilation task pending)