We have recently released a new video demonstrating a working FGPA, as well as additional GoldStrike1 ASIC chip details.
Tape-out due: 1st week of October
If you just got the FPGA to work, how can you complete the back-end trial-run, back-end final-run and functional verification in 1 week?
The Backend process has been going on for weeks. Functional verification is long done.
It is not a serial process. We are taping out 1st week of Oct.