Quote from: goodney on November 06, 2013, 06:28:11 PM

The FuryBug hashes!

Thought you guys might like an update on my little dev board. As you can see from the pictures I managed to mess up the schematic a little bit, hence the teeny-tiny blue wires. The Xacto knife is your friend.

I'm using KNK's cgminer fork which detects my single chip as a Bank 0, chip 0. Long term average 2GH/s.

FYI, gingernuts, the CPLD as a level shifter is genius. That would have saved me a ton of time.

Why do you have two chips for level shifting and what are they (can't see from the picture)?
For SCK and MOSI a resistor divider should be enough for single bank/chip. Also instead of the blue wires couldn't you just swap the wires going to the RPi at the top left of the board?

P.S. I have just uploaded another change to my fork which adds support to level shifters with active low for the OE too (like TI SN74AVC4Txxx).
The next step is support for line decodes for the OE (2:4, 3:8 or 4:16) - this way you can have (for example) 8 separate banks with just 3 GPIO's from RPi by simply using 74HC138 or 74HC238 depending on the level shifter in use