Re: [ANN] Bitfury is looking for alpha-testers of first chips! FREE MONEY HERE!
That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.
Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup
I would have liked to have c-scape in my design review to say 'you don't want to do it like that!'
That seems like a short coming or bug in the CPLD. A CPLD with 3.3V tolerant I/O shouldn't care what the state of the pins are when it powers up... which CPLD did you use?
Yeah, I'm a bit surprised they're so easy to damage...
I'm using a Xilinx xc2c64 - once I've swapped this dead one out, I'll make sure I take the 3.3v feed from the rpi.