Quote from: vs3 on November 08, 2013, 04:15:05 AM

Quote from: goodney on November 07, 2013, 07:20:49 PM

Quote from: gingernuts on November 07, 2013, 09:39:02 AM

That was my plan with the CPLD - 1.8v I/O within each board, 3.3v between them and the controller board.

Unfortunately I didn't think through the implications of powering the rpi independently of the 3.3v to the board during bring up - I wanted to be able to measure the board's 3.3v draw. Unfortunately if you power the rpi up before the board, you send 3.3v into an unpowered I/O pin on the CPLD and the chip goes into latchup Sad

I would have liked to have c-scape in my design review to say 'you don't want to do it like that!' Wink

That seems like a short coming or bug in the CPLD. A CPLD with 3.3V tolerant I/O shouldn't care what the state of the pins are when it powers up... which CPLD did you use?

which is why I picked to go with the KISS Principle - a few resistors, one transistor and that's all - very very few things to go wrong

Well, I was going for the more-integration => less to go wrong side of the KISS principle, seems your version was more successful this time round!