Quote from: Bicknellski on November 12, 2013, 02:56:27 AM

Mini-rant from our EE about the latest chip spec update:

1. Why are the designs less specific now Bitmine for the A1 chip?

2. Why haven't you specified the top-to-bottom pad distance, or completely specified the position of the 0.2mm wide pads that carry the signals. Why have you done this? Was it on purpose? Worrying very worrying.

Please note your package has pads only 0.2mm wide and by not specifying your position this leaves us open to losing half of EVERY pad, if we are off in our guesses by only 1/10th of a millimeter. Only 100 microns, right? Please note that adds to the chips professed tolerance in your positioning of 50 microns. This is shocking. You need to include ALL the dimensions in the picture and table as soon as possible.

3. In response to a request to move the signals to allow for a ground escape between pins 8 & 9, you have doubled down by newly assigning pin 8 to Vdd (pin 9, a long vertical pad that forms the other side of the requested escape, is also Vdd). And, unfortunately, the pinout drawing is only related to the package drawing, in shapes. We should be happy that, at least, you fixed their pin naming to match the descriptive table that accompanies the drawing but we need Bitmine to really put out documents that are helpful

4. We will not be hand assembling A1 chips to the boards. These chips require robotics to have any chance at all and forget about hot-air-rework - if one of these chips is failing, we will have to scrap the whole board, at worst, or ship it with blue-wires and degraded capability at best.

5. Your promise of replacement chips for failed ones won't begin to cover the costs of discarding the whole board. We are going to design in a physical bypass for every chip, even though that will reduce our density by 20% or more in order to protect those doing DYI and others who buy from us.

6. At this point given what we are learning from Bitmine we expect to have two-three re-spins of boards with these chips, before we get the footprint, solder stencil, and reflow curves right. That's four iterations before production... please Bitmine help us reduce that if at all possible by providing some decent chip specs. We want to have a reasonably good chance to succeed with your chips.

Thanks,

The Wasp Team

Hi,

Thanks for pointing these things out to us. Please rest assured that nothing has been made on purpose, it is in our obvious interest to help users and OEMs to build devices based on our ASIC, if it wasn't we wouldn't have released the specifications at all.

We forwarded your inquiries to our IC packaging house who's now updating the drawing with the missing quotes. The pins have been spaced a bit more in order to have more than 0.2 mm spacing between the pads on the footprint, as this could cause manufacturing issues when using 70um copper boards (which is a good thing given the very high currents involved). We also asked for footprint and solder paste recommendations.

A new specification will be published as soon as we have it,

Thanks