FPGAs and ASICs are very closely ralated, and FPGAs are generally used to prototype ASICs.
FPGA data + 500k$ = ASIC
Good luck 4% guy
Good luck 4% guy
Wait Wait.
You guys are saying that with the FPGA and bitstream code OP has, someone with deep pockets can actually produce an ASIC from it?
I believe you need the low-level source code (behavioral logic, transistor-gate level) to make an ASIC out.
Or you would have to reverse engineer the bit-stream which would also require complete knowledge about entire FPGA layout and schematics?
There isnt really much magic to the RTL for these things. Most of the performance gains are more about working around the nuances of the FPGA design and finding hardware where someone has laid out all the needed components (memory bandwidth and/or low latency memory, multiple chips with high speed interconnect, etc. I do wonder how the the OP intends to secure the bitstream if he distributed it. It would be pretty easy to write your own miner, and you can only encrypt the bitstream if it is your own hardware and you burn eFuses or similar.
Also with FPGAs and dev boards you are usually given very detailed manuals and all the schematics.
Anyone equipped to do ASICs could implement the algorithms themselves, its all about the capital - and accepting that all that cost is wasted if the algorithm is changed. For a lot of modern algorithms it is more about assembling the memory components than even the ASIC cores.
The reason some of us are long on FPGAs is they have the potential to be lower cost, much lower power, and higher performance than GPUs for algorithms that choose to resist ASIC development (aka change regularly). There is very little a GPU can do to gain advantage on modern (upcoming) FPGAs in that world. The transition to HBM as standard and Intel ending the artificial high price racket are the only barriers. It doesnt take that long to stand up working RTL for an algorithm change. Personally Im thrilled if Crypto pressure ushers in a whole new era of high performance computing.