Quote from: GPUHoarder on May 12, 2018, 03:36:16 PM

I get really skeptical at claims like 520MH ETH. Where is the 4TB/s of memory bandwidth coming from?

32 GB of installed memory = 130 GBytes/second per GB. If you go with the highest currently available pin rate (GDDR6), that would be 18Gbps per pin IO. 130GB/s -> 1 Tbit/s, so you need ~ 57 pins per GB of memory. Lets account for overhead and say 64. That means two chips per GB, or 4Gb 32pin Chips. 64 chips, and over 2048 I/O lines. Not impossible, but definitely a lot of chips/expense.

I think you made a mistake of taking their marketing materials literally. Their marketing people wrote seriously confused and non-physical stuff like "approx 900W to 1kW per hour." It also confuses single ASIC chip parameters with the overall system parameters.

Do you really think that they have in that box a single chip dissipating 1kW with 2 USB, 1 Ethernet and 1 HDMI port?

To me it is quite obvious that they must be proposing a system containing many much smaller chips. Why this couldn't be a system with 64 chips with 0.5GB of eDRAM in each chip? Reconfigurable cryptographic processors are now being researched and produced for about 20 years.

I wouldn't rush to judgment just based on a single marketing blurb. Have you ever played "deaf telephone" as a kid? This is a standard game being played in the meetings between R&D and marketing.

Edit:

Before I succeeded at posting the above I received a warning there was a new post from somebody directed at GPUhoarder saying something to the effect "redo the calculations with HMC or HBM". I think that post had disappeared due to forum bug or possibly self-censorship.

Could someone familiar with any of those technologies make another post with relevant calculations?

Thanks.

https://en.wikipedia.org/wiki/Hybrid_Memory_Cube
https://en.wikipedia.org/wiki/High_Bandwidth_Memory