Quote from: GPUHoarder on May 13, 2018, 02:21:09 AM

Quote from: greerso on May 13, 2018, 12:26:43 AM

Quote from: senseless on May 12, 2018, 08:04:24 PM

Lol, I don't code bitstreams myself Cheesy

-- I've got a basic understanding best case. It's also hard to stop from chattering when i'm so close to having half a purple coin.

If you dont code bitstreams yourself, how did you start fpga mining on AWS? Hire help?

Slightly pedantic, but bitstreams, from RTL via VHDL or Verilog are not strictly speaking programmed or coded.

Designed and implemented are probably better terms. Code / programs are usually statements of instructions to be executed sequentially by a processor (after being compiled or interpreted).

RTL describes the design of actual hardware interconnections / logic between registers, all of which happens essentially at the same time unless you setup clocks and registers to serialize iti. After being written (ok we can call it coded if you really want) and described in Verilog or VHDL it is synthesized, or turned into actual logic gates for the hardware in question - using the LUTs and flip-flops and such available on FPGAs or standard cells for ASICs. Once the synthesizer decides how the logic will be constructed, place and route figured out where to put it all on the chip and how to wire up the connections. The bitstream is actually just a list of every essentially possible connection point on an FPGA and whether or not it is connected. It isnt executed or run like a program. Programming the bitstream onto the chip would be more like handing an electrician a wiring blueprint and having them connect all the appliances, lights, outlets, etc. with wires according to it.

The more I learn, the more I realize how far I am from succeeding in fpga mining on AWS. I'll keep learning so that in a few weeks if the o.p follows through or the expert I have solicited to help becomes available, I'll at least know enough to have informed conversations.

Thank you for continuing to post this useful information, I feel like a few more posts and you fpga guys may let me in on the secret handshake.