Quote from: O_Shovah on July 17, 2011, 11:55:30 AM

[...]
I have contacted them already they would also give us a price quote if we send some gerber files of a nearly final design and a BOM so they would also do the assembley.

They also accept Eagle files, so no need for exporting anything.

Quote from: O_Shovah on July 17, 2011, 11:55:30 AM

Currently i am modifying your layout and routing to fit a 4 layer PCB. Acording to my knowledge alls unused IO pins are bound to ground by default so i changed this in your schematic.(please someone verify this).

I just checked: you are right, the default is pull down, pull up or floating is an option. The reason why I thought the default was pull up is the HSWAPEN pin: it enables pull ups during configuration. So during configuration, the choice is between pull up and floating. So there are several options:

All pins connected to VCCIO:
- Program pull ups in the bitstream: should work nicely.
- Leave bitsream at default pull-down: quite a power consumption during operation (bad choice).
All pins connected to GND:
- Program pull ups in the bitstream: quite a power consumption during operation (bad choice).
- Leave bitsream at default pull-down: quite a power consumption during configuration.

Quote from: O_Shovah on July 17, 2011, 11:55:30 AM

[...]
Saddly i asume there is no way to merge the egale layout files automatic.(this used to be a lot easier with Altium.... I am totaly new to Eagle) And the library of eagle is confusing me over and over again.
[...]

As long as the signal names are correct, you can merge files, it is just very cumbersome:

Open the first file, on the first sheet
GROUP all
CUT (0 0)
Open the second file, create a new sheet or go to the sheet where you want to place stuff.
PASTE, find a spot to place stuff (e.g. (0 0))
Save file.
Repeat for all sheets in the first file.

The above procedure has a minor fault if ICs are spread over more than one sheet (like in my design): once an IC is already present in the design, pasting in more gates of that IC will instead cause a new IC to be instantiated. You need to repair this manually, e.g.:

For each gate that has the wring IC name:
DELETE the gate
INVOKE the gate from the original IC
Place that gate at the position where the old one was: the connections are made automatically.