The 8mil line width and line spacing are a problem, though: I cannot get an 8mil wire between two pads of the FPGAs: the clearance is too small. This problem can be solved by using more vias and routing everything on the other layers, but is is less than ideal.
Out of interest, is 6mil trace + 6mil space good enough? That's what Laen's PCB group order for hobbyists provides, and supposedly someone's done a PCB with this pitch of BGA on that service. Of course, the turnaround times on that are probably less than ideal, especially if you're not in the US.
- What does pcbcart mean when they ask for the "Min. Annular Ring"? The width of the ring on one side ((D_via-D_hole)/2) or the sum of the width on both sides of the hole (D_via-D_hole)?
I'm pretty sure annular ring is generally defined as the width of the copper ring on each side, so D_via = D_hole + 2 * annular ring.