For example - there are 40 pins that provide IOVDD and IOVSS - do you really have to have 40 pins for that? Do they have to deal with that high currents?
Well, they do need quite some lines I think... Rough estimation is that @0.85V and 0.5W/Ghs they would need to have ~59 amps (100ghs*.5W / 0.85V) per chip (not including losses and such and assuming 1 chip per 100ghs device).
And the other question - heat - what are the plans to deal with that?
Is the silicon going to be exposed (BFL-like) where users can attach a proper heatsink? Or is heat going to be dissipated through the PCB? If the second then bitfury-like packaging with a huge pad underneath the chip (and tons of vias on the pcb) will be better than a bunch of balls/pins.
Yes, heat is going to be substantial, but 50W is not too crazy for a chip with a large heatsink. Pictures of testing heatsinks have been posted as Carlton is mentioning.
On the first question - you probably haven't looked at the specs. There is a separate set of VDD/VSS pins for the CORE - that's where the main current goes. Those are okay to be as many as needed (but also don't have to be more than the necessary).
The IOVDD/IOVSS part is for the interface portion - where the chip communicates with other chips - there isn't any noticeable current going there. I'd be surprised if more than 50mA goes through those.
As for the heatsink - I'm not talking about what they plan to put in their retail products. The question is specifically to the chip's packaging. The final product design is a consequence of the chip design.
If the chip has exposed silicon - they you'll see heatsinks on top of the chip (e.g. like BFL). If the chip is meant the send all the heat via the PCB - then you'll see a large heatsink on the back of the PCB (e.g. like Avalon and Bitfury).
So - the question is which of the two options have they picked (and if that's been decided already).