Post
Topic
Board Development & Technical Discussion
Re: Modular FPGA Miner Hardware Design Development
by
Olaf.Mandel
on 20/07/2011, 12:38:48 UTC
With blind vias it'd be easier to put gnd on the 2nd layer and route the gnd pins down to that, it's not strictly necessary though. Can you finish routing up the rest of the board? It's pretty close to done. Look in the main folder.

We still need a clk source and MSP430 hooked up. I've freed up 1 layer of the board, so that should make things easier. We'd need the FPGA and MSP guys to come in now and offer some input on how best which IOs go where and the clock source.

I may get to it tonight.

For a clock source: you will probably need two: one for the FPGA, one for the MSP430. For the FPGA, I suggest the ASEM1-100.000MHZ-LC-T: it's small (3.2x2.5mm2) and should be sufficiently stable. For the MSP430, it seems a 25MHz source is needed, like the ASEM1-25.000MHZ-LC-T.

I am not very happy with using a "normal" crystal, because they are much larger then these SMD-MEMS oscillators. One question I am not sure of: can we maybe get away with feeding the FPGA only 25MHz? Then we could save one oscillator.