Quote from: krnlx on May 26, 2018, 01:47:21 AM

Quote from: GPUHoarder on May 25, 2018, 10:41:45 PM

Youve made two very aggressive anti-FPGA posts. Can you share your credentials and experience leading you to make such statements, or demonstrate why these things are not possible? Youve made at least 4 claims that I personally know to be untrue.

Not agressive, pessimistic. FPGA cards like that exists from 2014 https://www.alpha-data.com/dcp/products.php?product=adm-pcie-ku3
Many people(in Russia) pm'ed me and ask about this. They read this topic and think that it will be a GPU replacement.

Quote from: GPUHoarder on May 25, 2018, 10:41:45 PM

made at least 4 claims that I personally know to be untrue.

lyra2z will not fit fully pipelined (corrected). All other algos in my post _can_ be fitted and managed to run on fpga, but they will be to slow to ROI $4000 ($5000 soon) board.

Anyone that thinks that FPGAs are going to destroy GPUs 10x is wrong, but being 10-200% more power and cost efficient total ROI - yes, thats going to happen. I had a good conversation today I wish I could share, but sufficient to say that there are forces actively working to make sure the above remains true, and FPGAs have plenty of margin to play with to make that happen and continue to happen - GPUs have no room to move.

There are also some major developments over the last 4 years. The 16nm vs 20nn fabric is a big changer, and if you look at the old spartix 6 night and day. SERDES speed is light years different now, to the point that the amount of logic that can fit on a single chip is absolutely not an issue. For every chip to chip pair you can handle 50+ internal bus bits at full fabric speed. Hard resources and URAM and even BRAM have exploded. FPGAs have gotten better, cheaper, and faster much more than GPUs have.

The last open piece is high bandwidth access to big memory. It does exist now, but you have to architect it into your system. Within two years it will be there and there will no longer be a difference for that part.

I also dont think FPGAs are a centralization risk like ASICs, and as long as they remain closely competitive third hardware option I dont think there will be a reason for teams to explicitly resist them. I havent gained a full sense of where the community stands in that however.

Edit: are you trying to fit the whole chain in static logic fully pipelined? Lots of efficiency trade offs you make to do that, and it is not strictly necessary. Chip to chip FPGAs or look at partial reconfiguration options. Gains are possible.