Quote from: ilia_2s on May 30, 2018, 09:37:10 AM

Quote from: melpheos on May 30, 2018, 08:37:18 AM

Quote from: ilia_2s on May 30, 2018, 08:23:38 AM

Quote from: patata on May 29, 2018, 10:59:36 PM

Anyone know what the plan and time frame for x16r support are?

Hi. The X16 is a chain of 16 algos. There is no one FPGA-chip have enough resources (logic cels) to place a X16.

You need two chained but the dev must have some serious FPGA Kungfu skill

There is no any special "KungFu" for it. Maximum hashrate will be limited to FPGAs interconnection (transceivers bandwidth, FiFo buffers etc.). Therefore, Final Interconnection bandwidth have a 10-100x less speed than actual hashrate in one chip.

Sorry this is not correct. The bandwidth between the two FPGA's is 320GBps which supports the 512 bit intermediate result x 625MHz, so the hash rate of two FPGA's connected does not suffer from the interconnect.