Quote from: magik on July 23, 2011, 04:39:39 PM

With what I'm used to that sounds perfectly fine. We use a 100 MHz crystal - and the PLL/DCM can easily turn that into 100 or 50 using the least noisy clk0 output, and we can get all kinds of different ranges with the clkfx output - multiply the clock or reduce it in IIRC any integer between 1-256 over 1-256

I'm just unsure of what clock levels we can obtain we the hashing code. You know, I'll try to run some compiles right now and see what we can get, but now that I think about it yeah, if someone else said they had it running around 100Mhz then that sounds about right, we can tune from there.

There's a lot more projects in that open source fpga miner github now heh.... hrm.... i should probably go read that thread again

btw if anyone wants to read up on it:
Spartan 6 FPGA Clocking Resources
http://www.xilinx.com/support/documentation/user_guides/ug382.pdf

I had a quick try, and without any optimizations it was able to reach 50MHz. 100MHz is pretty certainly doable, and there are even reports that, with proper optimizations, a 190MHz synthesis would succeed in like 5% of the attempts. To reach optimum performance, it's very likely that we'll need CLKFX.