Power in a circuit scales linearly with clock speed and exponentially with voltage.
P = capacitance * voltage^2 * frequency
The reason why thermals spiral out of control at high clock speeds is because you also have to keep cranking up the voltage to keep things stable as the clocks go up.
I didn't think this is different for FPGA. Is it?
If that holds true, dropping the voltage on the FPGA to 0.75V from default 0.85V will allow for about 125% of baseline unmodified performance by allowing 25% OC within the same thermal envelope, assuming it is stable. So maybe about 11GH/s per card.
Whitefire is undervolting the card. He explained why in discord, but I can't recall the statement off the top of my head. But, I'm pretty sure this is why his amperage is so high.
We're going to bring up the modifications he mentioned to Xilinx and see how they feel about them. Some of the modifications we can do on our end before shipping (such as programming the PMBUS).