[...]
We still need to put in the clk sources as well.
I suggest 100Mhz with a 2.5v oscillator module, on pin IO L40P GCLK11 M1A5 (each FPGA has 1).
I already suggested a suitable MEMS oscillator before:
[...] For the FPGA, I suggest the
ASEM1-100.000MHZ-LC-T: it's small (3.2x2.5mm
2) and should be sufficiently stable.
[...] The design as it is on dropbox and github calls for the clock to be connected to IO_L30N_GCLK0_USERCCLK_2, pin AB13. The clock is shared between the two FPGAs (no need to have a dedicated clock for each). I will put the oscillator into the design, so it is no longer routed to the MCU.
Edit: I looked at the routed PSU, you might want to put some vias under the LMZ modules to better sink heat away from the thermal pad. In fact you could use unused layers in the board to make a more effective heatsink as well.
Can do that, but wasn't there the comment that putting vias onto pads causes problems during manufacturing? And eagle doesn't like it at all (a lot of drc errors).