Quote from: li_gangyi on July 27, 2011, 04:44:28 AM

Quote from: Olaf.Mandel on July 20, 2011, 12:38:48 PM

[...] For the FPGA, I suggest the ASEM1-100.000MHZ-LC-T: it's small (3.2x2.5mm²) and should be sufficiently stable. [...]

The oscillator you've suggested runs @ 3.3V, we'd need a 2.5V unit.

You are right, didn't pay attention to that. But the ASEMB-100.000MHZ-LY-T is a 2.5V capable oscillator that has 10ppm accuracy (enough?). The matching 25MHz oscillator is ASEMB-25.000MHZ-XY-T (higher temperature range, but the -LX-T version is non-stock at Diikey).

Quote from: li_gangyi on July 27, 2011, 04:44:28 AM

Quote

The design as it is on dropbox and github calls for the clock to be connected to IO_L30N_GCLK0_USERCCLK_2, pin AB13. The clock is shared between the two FPGAs (no need to have a dedicated clock for each). I will put the oscillator into the design, so it is no longer routed to the MCU.

I'm not sure how you plan to do this, to do it properly you'd need to buffer the oscillator and/or series termination at each end to reduce reflections.
[...]

I planned to just connect the oscillator to the pins and have a Thevenin termination on the other end of the line. pusle suggested to remove the termination and instead put a resistor (which value?) between the oscillator and the FPGA pins. What are your suggestions?