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@O_Shovah: You still have some trouble with using eagle. Some of your wires were not connected to the pins they touched. The order is important here: either place a part on top of existing wires or draw a wire to touch a pin. Moving a wire to touch a pin does not work. Also, you cannot change the signal carried by a wire by placing a suitable label close to it. You need to use the NAME command. It is usually a good idea to first use the label command to actually get the name displayed and then use the NAME command to change it and see the change in the label.
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I m sorry for making you clean up my mistakes. I hope i produce more advance than work.@O_Shovah: You still have some trouble with using eagle. Some of your wires were not connected to the pins they touched. The order is important here: either place a part on top of existing wires or draw a wire to touch a pin. Moving a wire to touch a pin does not work. Also, you cannot change the signal carried by a wire by placing a suitable label close to it. You need to use the NAME command. It is usually a good idea to first use the label command to actually get the name displayed and then use the NAME command to change it and see the change in the label.
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I just read through the MSP430 docu and found two things:
Good news: multiple SSEL signals are no problem. The STE signals provided by the serial engine are different from the SSEL signals. They are to facilitate multiple masters on one bus, so we don't need them. This means we can set UCMODEx=00 (3-wire mode) in both UCA1CTL0 and UCB1CTL0.
Bad news: the way the two serial engines are multiplexed onto the output pins, it is impossible to configure one engine to 4-wire mode and use the second engine at the same time. We don't need to to that, but this raises the question if two concurrent 3-wire SPI engines on the same port are even possible at all. Can anyone who knows their MSP430 forward and backward answer this? Alternatively we could use a 64-pin package (the 5510IRGC).
Good news: multiple SSEL signals are no problem. The STE signals provided by the serial engine are different from the SSEL signals. They are to facilitate multiple masters on one bus, so we don't need them. This means we can set UCMODEx=00 (3-wire mode) in both UCA1CTL0 and UCB1CTL0.
Bad news: the way the two serial engines are multiplexed onto the output pins, it is impossible to configure one engine to 4-wire mode and use the second engine at the same time. We don't need to to that, but this raises the question if two concurrent 3-wire SPI engines on the same port are even possible at all. Can anyone who knows their MSP430 forward and backward answer this? Alternatively we could use a 64-pin package (the 5510IRGC).
So that verifiys my first impression.
I also considered the 64 pin package. I doesn't need much more space and would provide plenty of additional pins with the second block for SPI in the 5510.
And we should also consider the case of using more than 2 FPGA's.