Well, as pure SW guy I can provide only limited HW related feedback, so please double check.
I have both a level shifter and the option to use an inline resistor to drop the 3.3V signal down to 1.8V on my test board similarly to how some Bitfury designs have implemented it. Have you investigated doing that, or just feeding 3.3V straight in?
I understood that the eval board used in China (the one you saw in the pictures) for testing has a level shifter for input and output signals, while Bitmine's boards use resistors to lower the input signals and a level shifter for the output signal (MISO) - seem to work both.
If we're working on a DIY board for the A1, how do we get in the queue for sample chips?
can you clarify the clock frequency required for the PLL. On the datasheet it quotes either 12MHz or 32MHz. Will either 12MHz or 32MHz give access to the full PLL range, or would the option of selectable external clocks in the 12-32MHz range be useful?
The queue was required for the very first sample chips with limited availability. Following waves will be available in volumes and should not need to register.
As for the clock: the eval board in China uses 12MHz clock, Bitmine's 16MHz - both work. PLL settings allow arbitrary setting of divider, configuration tables for the PLL settings for 12 and 16MHz input clock and different system clock rates will be added to the documentation ASAP. If you design a multi-chip board, to feed all chips with one oscillator you need - guess what - clock buffers (no kidding here).
Cheers,
zefir