My (2) DR3 are hashing 2+ days since PDU reset, but i have seen my first one that i had since monday reboot on its own a few times. I'm holding about 8.5 - 8.7 TH/s confirme by pool side too. About 3.5 % HW errors though.
I've got frequency maxed on both at 450, Chip temps are ranging from I:56 O:78 on worst chip, and I54 O:72 on the best. PCB is i:45 O:63
I see the same kernel log items you do doesnt seem to be an issue No reboots in 2+ days though. I'm using BTC.com pool to china, from USA (not the best idea but it was a quick one to get started with)
Oct 4 22:32:54 (none) local0.warn cgminer[950]: Chain 0 set_temperature_offset_value_chain_sensor
Oct 4 22:32:54 (none) local0.notice cgminer[950]: set_temperature_offset_value_chain_sensor: Chain0 Sensor0 temp offset : 05,
Oct 4 22:32:54 (none) local0.notice cgminer[950]: chain:0 local:36 remote:35
Oct 4 22:32:54 (none) local0.warn cgminer[950]: Chain 0 set_temperature_offset_value_chain_sensor
Oct 4 22:32:55 (none) local0.notice cgminer[950]: set_temperature_offset_value_chain_sensor: Chain0 Sensor0 temp offset : 06,
Oct 4 22:32:55 (none) local0.notice cgminer[950]: chain:0 local:41 remote:38
Oct 4 22:32:55 (none) local0.warn cgminer[950]: Chain 0 set_temperature_offset_value_chain_sensor
Oct 4 22:32:55 (none) local0.notice cgminer[950]: set_temperature_offset_value_chain_sensor: Chain0 Sensor1 temp offset : 03,
Oct 4 22:32:56 (none) local0.notice cgminer[950]: chain:0 local:41 remote:40
Oct 4 22:32:56 (none) local0.warn cgminer[950]: Chain 0 set_temperature_offset_value_chain_sensor
Oct 4 22:32:56 (none) local0.notice cgminer[950]: set_temperature_offset_value_chain_sensor: Chain0 Sensor1 temp offset : 04,
Oct 4 22:32:56 (none) local0.notice cgminer[950]: 1 calibration_sensor_offset_chain
Oct 4 22:32:56 (none) local0.notice cgminer[950]: chain:1 local:35 remote:29
Does yours also state in the kernal log about - -
Trying to unpack rootfs image as initramfs...
rootfs image is not initramfs (no cpio magic)
And
nand: WARNING: pl35x-nand: the ECC used on your system is too weak compared to the one required by the NAND chip
Bad block table found at page 131008, version 0x01
I don't have a dr3, just trying to see if there's a underlying issue