Quote from: JaredKaragen on January 28, 2019, 03:27:17 AM

im going to be the skeptic; don't take it the wrong way.

Why arent you doing this? :

Quote from: yohan on November 14, 2018, 08:10:04 AM

The expected production process is as follows:
(2) Gather enough pre-orders to be viable - aim over next 1-2 weeks.
(1) Give out full details of product and offer.
(3) Payment for pre-order/ hard commit by customers.
(4) First production boards get delivered approximately 8-10 weeks after stage (2)/(3). We will try to better this but this number determined by our parts suppliers.

Things such as currently working bitstreams, guarantee of algos that will be available by what date (specifically) as well as hash to power figures....

As of this point; in this day and age; you should have at least a physical demo and review of the hardware verified by a heavily trusted member before taking in any funding.... as in the past; taking in funds before us seeing some actual results on this website from a trusted reviewer, has almost always resulted in disaster of many different levels and proportions.

At first glance, I see a big up front hardware cost; with no promise of return other than a stated interest in algos (no word on active development or working hashing bitstreams for instance...); especially since you mention algos that are constantly changing to be as asic/FPGA resistant as possible... we aren't not even any sort of efficiency datum or anything; just a spec sheet for a publicly sourceable fpga.

The hardware looks like it should be very versatile; and it looks like the product as shown is a sound concept/design.. but; you are asking a bunch of people to jump off a cliff right now without knowing if there's a parachute attached to their back while boarding the plane.

I hope you understand my concern, and its meant in the best of light to help you succeed. These are the main red flags I have to share and ask about.

Fair points and stages 1,2,3 have stretched out for a combination of reasons. The first part of this was it took us longer to complete the initial design than anticipated and that was mainly due to us having to redesign the controller and power sections a few times to shrink circuit size and to allow running at higher power levels as requested by our potential bitstream providers. The next part of the delay was the crypto wobble we saw in late 2018 and we ourselves took a few weeks to evaluate the situation and basically delayed building dev boards and going forward to making the offer to customers. The same wobble also meant that it has taken longer to get to the critical mass of orders. We also slipped in a large unrelated rush customer job to improve our funding and give us more options on how we did the build.

The next part of what is happening is that we are mainly reliant on outside developers for bitstreams. We do have a very junior member of our team doing an initial first algorithm backup it needs one of our senior people to be free to help get that running. This option was only ever meant to be a last resort and our senior team focus is still on the evaluation of the Issue1, getting Issue 1.1 to developers, and the now running customer build. External devs are delayed on lack of hardware and basically overloading and of course this is a concern. However in the worst scenario we can simply turn most our very experienced FPGA team to algorithm development and that will happen about late February/early March should no other bitstreams be available. We do have have public statements by Whitefire/Zetheron on Discord stating they will be providing bitstreams and they are just one of several devs working with us.

The main FPGAs are not a secret on the design and there is more on this in Discord but they can actually be read off the block diagram available on the product webpage. They are Intel Arria10 GX1150 and there are two of those on board. Arria10 selection table giving resource outline here - https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/pt/arria-10-product-table.pdf . The board has a USB hub inbuilt and off that an inbuilt JTAG programmer that works directly with Intel Quartus tools. That's the crude programming mechanism. The on board Cyclone5 SoC will run Linux and offer a pile of other bitstream loading options.

We did consider forms of escrow with senior member community but we have difficulty in justifying the costs given out low margin and also that we are a reputable business trading for 30 years next month without any black marks on our record. That's public record if anyone cares to look it up and a longer public record than pretty much anyone else in crypto community. The crypto community also has a lot of experience in our previous product Cairnsmore1 from 2012/2013 where we used a very similar product launch mechanism and dare I say lots of people made good money out that product. Nobody lost out with us on that development. On the CM1 development/product launch we took peoples funds, we kept to timeline pretty much, and external developers delivered bitstreams in time for the first boards shipping. That was before external developers even had a monetary reason to do the work which is one major change today with dev fees being common practise.

We have recognised early customers risk with an extended purchase discount scheme going forward and there will be a more formal structure coming for that in the next few weeks.

Hope that explains where we are on this project to everyone here. I'll be happy to answer questions as soon as I see them although there may be more delay on here versus the cairnsmore5 email address or on Discord as I have to reconfigure my email alerts here. Just one of many jobs on my task list currently.