Quote from: eldentyrell on September 21, 2011, 04:41:12 AM

Just curious: are you actually mining on the chip, or is this just confirmation that the JTAG works and you're able to upload a bitstream?

I ask because designing a stable, properly-decoupled power supply for FPGAs isn't always easy... although for something as small as an LX25 you can get a way with a whole lot. The Spartan6-150 with a full chip design (~50% LUT/FF usage) at a decent clock rate will be a good test.

PS, speaking of clock rate, where's the clock signal coming from?

It'll be another 1-2 days before the 6s25 is mining; I'm still finishing the RTL + SW.
I was so excited that the BGA assembly worked that I couldn't wait to share Grin

On the 6s150, I'm waiting for the carrier PCB to come back from fab. With luck, there
won't be any power supply issues. In some ways, miners are simpler and less demanding
than many other FPGA designs: VCCInt power consumption is almost constant once it's
running, and there isn't much IO activity [OTOH, VCCInt power consumption is very high...]

To minimize cost, the clock is provided by the MCU PLL & clkout pin.

The FPGA is downloaded by the LPC MCU over USB (slave serial).
The AVR board + USB serial cable is just there to provide power,
and program the LPC.

-rph