Quote from: gopher on October 11, 2011, 02:20:37 PM

Quote from: rph on October 03, 2011, 06:15:59 AM

Just a quick update - I've started work on a new multi-FPGA carrier design.
Time to stop messing around, and build something badass. Grin

-rph

rph, great work, I have finally find courage to subscribe to this thread...

I have couple of comments/suggestions.

Have you though of adding ETH PHY and SD card modules to the carrier board so once the bit-stream is uploaded (written on the SD), the unit could be set to survive hardware reset and run fully autonomously?

I am sure implementing compact TCP/IP stack and HTML server on the FPGA would not be that difficult (many available open source examples out there), and the required Bitcoin function, to feed the hashes to the FPGA and then feed the result back to a pool, should be relatively easy to code, re-write one of the better Python miner-scripts.

Also, with regards to the efficiency of the core - correct me if I understand this wrong - I see that professional outlets achieve 2.4 Gh/s with a Spartan 6 -3 (at least that is what I conclude after reading the document posted here http://www.heliontech.com/downloads/fast_hash_xilinx_datasheet.pdf#view=Fit - and that is way more efficient compared to the various FPGA implementations discussed on the bitcointalk.

Otherwise - the mere fact that you guys already achieved capital cost of $1/Mh in single chip quantities (that's what my highly-cost-optimised GPU rigs cost me, in QTY>10) indicates that you are on the right track - and things can only improve from here.

if your refering to "max SHA-1 rate 2041 Mbps 1542 Mbps 2578 Mbps"

I am not sure if Mbps equates to Mhash/s . first I dont know if they mean Mega bytes per sec, or mega bits per sec, but it is definitely not mega hashes per sec.

Please someone jump in here who knows... because this helion chip would be HUGE>