Quote from: Syke on April 24, 2014, 01:24:03 AM

Quote from: 2112 on April 24, 2014, 01:18:49 AM

This has already been discussed numerous times: only Bitfury used the proper design flow for the mining chip: BSIM (or equivalent analog/mixed-signal) simulation, but this was his first ASIC project.

I would so love to see him do a 28nm shrink.

Bitfury can't just shrink his design. He did full-custom 55nm drawn transistors with 65nm nominal process. But at least he was knowledgeable enough to point my mistake that BSIM4 models are not required for his process, BSIM3 are enough.

My best guess is that everyone else (who did unrolled cores) used standard-cell low-power design flow and crude modeling/simulation tools that usually accompany digital synthesis tools.