Quote from: valhs on Today at 08:41:48 AM

Thank you for the miner.

I have two questions.

In zergpool is for algorithm yespowerTIDE also the miner cpuminer-opt-24.4 mentioned.
Is it a different cpuminer-opt than the one in this thread or which paramater enable that algorithm?

The code is prepared for risc-v and not yet activated.
There exist already reasonably priced cpus, e.g spacemit in Banana BPI-F3, which support the SIMD instruction RVV.
Will cpuminer-opt support soon risc-v and maybe use 'SIMDe - SIMD-everywhere' solution or sse2rvv?

You're welcome.

cpuminer-opt can mine any yescrypt or yespower coin by specifying the parameters. See https://github.com/JayDDee/cpuminer-opt/wiki/Supported--Algorithms.

The parameters are part of the coin's specification and should be published by the coin's developpers. Tide chose not to publish the parameters,
in their mining guide, however I found the parameters buried in the code:

Code:

int scanhash_tidecoin_yespower(int thr_id, uint32_t *pdata,
const uint32_t *ptarget,
uint32_t max_nonce, unsigned long *hashes_done)
{
static const yespower_params_t params = {
.version = YESPOWER_1_0,
.N = 2048,
.r = 8,
.pers = NULL,
.perslen = 0
};

Simply add "-N 2048 -R 8" to the command line and it will mine Tide. Pers (-K) is left at the default of NULL.

RISC_V is another story. Pi is not a viable mining platform, whether ARM or RISC-V. ARM now has Apple and Snapdragon-X
that produce more powerful CPUs but they only perform as a light desktop. They can't compare with Intel Core or AMD Ryzen.

On the HW side the most interesting thing for RISC-V is the HiFive P550: https://www.sifive.com/boards/hifive-premier-p550
but the CPU Is still very weak.

On the SW side all the vector code would have to be rewritten for RISC-V. Translation layers like sse2neon (for ARM) don't cut it.
They only provide compatibility by emulating SSE instructions using NEON. Performance is terrible.

I'm still trying to understand ARM SVE with uses vector length agnostic programmimg, meaning the code doesn't know the size of
the vector registers and can't be optimized for the HW. Tuning SVE for a particular vector length is critical for cpuminer-opt but it
will add run time overhead which will affect it's performance. It will likely also require a complete rewrite of all vector code in cpuminer-opt.
This is a lot more complex that implementing NEON. RISC-V is also vector length agnostic but I don't yet knw how its implemented.

The short answer is no RISC-V anytime soon if ever.

On a tangent, Bitmain released a XMR miner that actually uses a cluster of RISC-V CPUs. Some people mistakinly call it an ASIC but it's just CPUs.
AFAIK it hasn't sold well.