Quote from: DeathAndTaxes on May 05, 2014, 12:04:07 AM

Quote from: BurtW on May 04, 2014, 10:53:35 PM

SSD is at 8 electrons per bit so only three more very very difficult doublings.

Not sure where you get this idea from. SSD are NAND transistors. Even at 20nm the transistors are 30 to 40 atoms across and each Silicon atom has 14 atoms. Of course even that really isn't material. No silicon circuit works on individual electrons. Retrieving or writing a bit of flash ends up involving millions of electrons.

Maybe you are conflating MLC and TLC (storing two or three bits per cell) with number of electrons? Not sure.

A flash cell is a special transistor with a floating gate. It is like a very tiny capacitor. The difference between the charged state and the uncharged state is used to represent/store a 1 or a 0 in SLC flash or on a MLC flash various charge levels are used to represent the stored information. The floating gate itself is made of a small piece of material that may have a lot of electrons but it is the extra electrons that are pushed on the gate when charged that I am talking about.

I am a bit mad at myself because it looks like I was wrong. I could have sworn I had a reference that showed that sub 20nm flash was sub 10 electrons on the floating gate in the charged state. I cannot find that reference. The reference I did find here:

http://www.eecs.berkeley.edu/~tking/theses/whkwon.pdf

in figure 1.14 still shows 10's of electrons on the floating gate all the way down to 10nm.

My point that the feature size does have a physical limit is valid and eventually we will run into this physical limit.

The absolute limit for this technology (storing information by charge on a floating gate) would be one electron per bit.