Next scheduled rescrape ... never
Version 2
Last scraped
Scraped on 30/07/2025, 12:05:55 UTC
Again, there is no such thing as an "open source secure element". Only the firmware can be open source. You call it nitpicking but this is a crucial difference.
I don't care about your opinion, so if you don't like what I posted or you don't understand it than simply ignore it.There are secure elements that are fully closed source, and those that are open source partialy.
This is not my opinion, but a factual information.
Quote
Tropic Square is the closest thing to an open-source secure element that actually exists in silicon, but it’s still a work-in-progress, not a shipping product.
Project status
• First silicon (TS-1) taped-out 2023 on GlobalFoundries 28 nm.
• Second tape-out (TS-2, with fixes and more crypto) targeted mid-2025.
• No public release date for purchase; Trezor is using early lots internally.
What is open
• Entire RTL (SystemVerilog): AES, SHA-2/3, ECC, TRNG, PMP, side-channel counter-measures.
• Formal proofs for masking and fault-injection resistance.
• Complete GDSII → netlist → layout → DRC/LVS flow scripts.
• Host driver code © and Python bindings on GitHub under GPL-3.0.
What is NOT open
• The actual 28 nm process PDK (NDA with GF).
• Final packaging and tamper-mesh details.
• Certification artifacts (FIPS 140-3, Common Criteria) will remain confidential even if the chip passes.
Project status
• First silicon (TS-1) taped-out 2023 on GlobalFoundries 28 nm.
• Second tape-out (TS-2, with fixes and more crypto) targeted mid-2025.
• No public release date for purchase; Trezor is using early lots internally.
What is open
• Entire RTL (SystemVerilog): AES, SHA-2/3, ECC, TRNG, PMP, side-channel counter-measures.
• Formal proofs for masking and fault-injection resistance.
• Complete GDSII → netlist → layout → DRC/LVS flow scripts.
• Host driver code © and Python bindings on GitHub under GPL-3.0.
What is NOT open
• The actual 28 nm process PDK (NDA with GF).
• Final packaging and tamper-mesh details.
• Certification artifacts (FIPS 140-3, Common Criteria) will remain confidential even if the chip passes.
Quote
Infineon OPTIGA Trust M
Publicly available: command reference, host-side drivers (MIT-licensed), example code.
Everything inside the secure element—RTL, ROM mask, crypto microcode—closed and NDA-gated.
ATECC608C
Publicly available: datasheet, CryptoAuthLib (BSD-3), Arduino examples, Python wrapper.
Secure-element ROM, key-store format, and test vectors are proprietary.
Publicly available: command reference, host-side drivers (MIT-licensed), example code.
Everything inside the secure element—RTL, ROM mask, crypto microcode—closed and NDA-gated.
ATECC608C
Publicly available: datasheet, CryptoAuthLib (BSD-3), Arduino examples, Python wrapper.
Secure-element ROM, key-store format, and test vectors are proprietary.
You actually need to have functional brain to understand this table, but I think even average gorilla would understand meaning of this image from my table, and what Open Source
Translation:
First row - hardware wallet name, Second row - open source code.
Version 1
Scraped on 30/07/2025, 11:41:07 UTC
Again, there is no such thing as an "open source secure element". Only the firmware can be open source. You call it nitpicking but this is a crucial difference.
I don't care about your opinion, so if you don't like what I posted or you don't understand it than simply ignore it.There are secure elements that are fully closed source, and those that are open source partialy.
This is not my opinion, but a factual information.
Quote
Tropic Square is the closest thing to an open-source secure element that actually exists in silicon, but it’s still a work-in-progress, not a shipping product.
Project status
• First silicon (TS-1) taped-out 2023 on GlobalFoundries 28 nm.
• Second tape-out (TS-2, with fixes and more crypto) targeted mid-2025.
• No public release date for purchase; Trezor is using early lots internally.
What is open
• Entire RTL (SystemVerilog): AES, SHA-2/3, ECC, TRNG, PMP, side-channel counter-measures.
• Formal proofs for masking and fault-injection resistance.
• Complete GDSII → netlist → layout → DRC/LVS flow scripts.
• Host driver code © and Python bindings on GitHub under GPL-3.0.
What is NOT open
• The actual 28 nm process PDK (NDA with GF).
• Final packaging and tamper-mesh details.
• Certification artifacts (FIPS 140-3, Common Criteria) will remain confidential even if the chip passes.
Project status
• First silicon (TS-1) taped-out 2023 on GlobalFoundries 28 nm.
• Second tape-out (TS-2, with fixes and more crypto) targeted mid-2025.
• No public release date for purchase; Trezor is using early lots internally.
What is open
• Entire RTL (SystemVerilog): AES, SHA-2/3, ECC, TRNG, PMP, side-channel counter-measures.
• Formal proofs for masking and fault-injection resistance.
• Complete GDSII → netlist → layout → DRC/LVS flow scripts.
• Host driver code © and Python bindings on GitHub under GPL-3.0.
What is NOT open
• The actual 28 nm process PDK (NDA with GF).
• Final packaging and tamper-mesh details.
• Certification artifacts (FIPS 140-3, Common Criteria) will remain confidential even if the chip passes.
Quote
Infineon OPTIGA Trust M
Publicly available: command reference, host-side drivers (MIT-licensed), example code.
Everything inside the secure element—RTL, ROM mask, crypto microcode—closed and NDA-gated.
ATECC608C
Publicly available: datasheet, CryptoAuthLib (BSD-3), Arduino examples, Python wrapper.
Secure-element ROM, key-store format, and test vectors are proprietary.
Publicly available: command reference, host-side drivers (MIT-licensed), example code.
Everything inside the secure element—RTL, ROM mask, crypto microcode—closed and NDA-gated.
ATECC608C
Publicly available: datasheet, CryptoAuthLib (BSD-3), Arduino examples, Python wrapper.
Secure-element ROM, key-store format, and test vectors are proprietary.
You actually need to have functional brain to understand this table, but I think even average gorilla would understand meaning of this image from my table, and what Open Source id referring to:
Translation:
First row - hardware wallet name, Second row - open source code.
Original archived Re: Secure Element in Hardware Wallets
Scraped on 30/07/2025, 11:36:30 UTC
Again, there is no such thing as an "open source secure element". Only the firmware can be open source. You call it nitpicking but this is a crucial difference.
I don't care about your opinion, so if you don't like what I posted or you don't understand it than simply ignore it.There are secure elements that are fully closed source, and those that are open source partialy.
This is not my opinion, but a factual information.
Quote
Tropic Square is the closest thing to an open-source secure element that actually exists in silicon, but it’s still a work-in-progress, not a shipping product.
Project status
• First silicon (TS-1) taped-out 2023 on GlobalFoundries 28 nm.
• Second tape-out (TS-2, with fixes and more crypto) targeted mid-2025.
• No public release date for purchase; Trezor is using early lots internally.
What is open
• Entire RTL (SystemVerilog): AES, SHA-2/3, ECC, TRNG, PMP, side-channel counter-measures.
• Formal proofs for masking and fault-injection resistance.
• Complete GDSII → netlist → layout → DRC/LVS flow scripts.
• Host driver code © and Python bindings on GitHub under GPL-3.0.
What is NOT open
• The actual 28 nm process PDK (NDA with GF).
• Final packaging and tamper-mesh details.
• Certification artifacts (FIPS 140-3, Common Criteria) will remain confidential even if the chip passes.
Project status
• First silicon (TS-1) taped-out 2023 on GlobalFoundries 28 nm.
• Second tape-out (TS-2, with fixes and more crypto) targeted mid-2025.
• No public release date for purchase; Trezor is using early lots internally.
What is open
• Entire RTL (SystemVerilog): AES, SHA-2/3, ECC, TRNG, PMP, side-channel counter-measures.
• Formal proofs for masking and fault-injection resistance.
• Complete GDSII → netlist → layout → DRC/LVS flow scripts.
• Host driver code © and Python bindings on GitHub under GPL-3.0.
What is NOT open
• The actual 28 nm process PDK (NDA with GF).
• Final packaging and tamper-mesh details.
• Certification artifacts (FIPS 140-3, Common Criteria) will remain confidential even if the chip passes.
Quote
Infineon OPTIGA Trust M
Publicly available: command reference, host-side drivers (MIT-licensed), example code.
Everything inside the secure element—RTL, ROM mask, crypto microcode—closed and NDA-gated.
ATECC608C
Publicly available: datasheet, CryptoAuthLib (BSD-3), Arduino examples, Python wrapper.
Secure-element ROM, key-store format, and test vectors are proprietary.
Publicly available: command reference, host-side drivers (MIT-licensed), example code.
Everything inside the secure element—RTL, ROM mask, crypto microcode—closed and NDA-gated.
ATECC608C
Publicly available: datasheet, CryptoAuthLib (BSD-3), Arduino examples, Python wrapper.
Secure-element ROM, key-store format, and test vectors are proprietary.