Thanks, I am not spi usb programmer, Just want to help out, and keep you barking up the right tree 
Seems most industry devs already know most of this, It just hit the hobby level and I found it relevant to some of you guys diagnostic posts. AMT must also know this.
Seems all three have similar issues HF BA AMT. Would that boil down to Bitmine original design ?
1 SPI for each master slave.... Is correct way.
Seems most industry devs already know most of this, It just hit the hobby level and I found it relevant to some of you guys diagnostic posts. AMT must also know this.
Seems all three have similar issues HF BA AMT. Would that boil down to Bitmine original design ?
1 SPI for each master slave.... Is correct way.
Yes its a good point and most of have gone through that one, but in this we don't think it's the SPI. Zefir outlined this in his thread:
https://bitcointalk.org/index.php?topic=294235.0
The chip resets itself when:
A. when supply voltage is unstable,
B. chip gets too hot,
C. there is noise on SPI bus and communication gets messed up.
Once that happens, we have not found a way to get the chain back to life other then possibly issuing a HW reset which is covered in zefir's thread.
Along the SPI com lines... I've been wondering how that is being handled: The the SPI link that ISA posted a while back It says it *does* kinda allow addressing. 4 lines are available for that as I recall. Now as to if each addressed chip can be a master to more in a serial chain from it - dunna know. Gotta dig more.
Now even more relevant, from Zefir's thread: "I understood that the eval board used in China (the one you saw in the pictures) for testing has a level shifter for input and output signals, while Bitmine's boards use resistors to lower the input signals and a level shifter for the output signal (MISO) - seem to work both."
2 things on that: Just where is that level shifting done? and, Is it still being done with a resistor divider network?
Far far better to use a level shifter chip for both data out AND data in! By its nature using a resistor network makes the output signal from the divider highly dependent on what is fed in on the hi side and sensitive to the load presented by the A1. If either changes for any reason so does that signal level...
A level shifter chip not only changes the voltage but also acts as a Schmidt trigger (very tolerant to input signal level changes) giving very predictable switching as well as being a decent current source that will always deliver the specified output voltage regardless of load (within chip specs of course). End result is very clean data signals.
And also per that thread (and should always be done in ANY logic design until proven unneeded) Is the clock signal to each A1 buffered?