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Quote from: jonnybravo0311 on July 29, 2014, 02:03:08 AM

I won't go with "nothing". My answer is, "whatever is profitable enough to invest in ASIC design and development". So, if X11, or BobsMagicHashingFormula becomes the next big thing, then somebody will develop an ASIC for it. If there's money to be made, somebody's going to make it Wink

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Perfect answer. You will notice coins say asic resistant. They do not uses (or should not) proof. If there is a big enough market share there will be a product for it.

A n/x11 would be nice but I don't know if or timeline we will see that. Scrypt and of course SHA-256 are controlling the game right now.

In fact, an X11 ASIC was a project I wanted to take on. I'm well aware of the capital required to produce ASIC's but if the cost can be justified and an FPGA implementation followed by a few sample batches produced ( well under 500,000 USD I hope, but if costs get out of whack this is gonna be one hell of a project Cheesy

) I think the garnered interest could be used to develop one. Of course, I'm talking in very loose terms.

Making my own ASIC company has been a long time dream of mine. I've heard plenty of "you're not going to make it" or "somebody get rid of this noob" but I honestly don't care. Just gotta pull through. I'm just gathering some useful data for that venture Cheesy

If you can make a functional X11 FPGA miner, then is the step to a ASIC really not that big.

Well there's my first piece of optimistic news Cheesy

I know X11 uses 11 hashing algos ((blake, bmw, groestl, jh, keccak, skein, luffa, cubehash, shavite, simd, echo),
Some of these look like SHA-3's but the rest, I'm not so sure. In fact, I'm not even sure how X11 puts this all together.
Is data hashed through all of them sequentially or do certain algos get performed multiple times?
It feels like it could be paralleled although I think the GPU miner might have already done that.

Is there any way of converting the GPU CUDA/OpenGL code to FPGA or do you have to rough it and start from scratch?

X11 uses a lot of algorithms, but they are all FPGA/ASIC friendly, they may develop a semi-programmable system, where hash units can be chained together to be compatible with new variants (X13, ...).

I was thinking of an ASIC FPGA hybrid with X11 in ASIC and FPGA allowing further implementations. Just need to check the FPGA implementations of each alto and chain them somehow.