Quote from: mrpark on August 15, 2014, 01:24:57 PM

Quote from: Biffa on August 15, 2014, 10:39:35 AM

Quote from: hashfastisawesome on August 15, 2014, 04:41:26 AM

Quote from: Spondoolies-Tech on August 15, 2014, 04:10:19 AM

My vague statement was correct. I don't reveal the full details on purpose.
In about 45 days (October batch) the SP30 will be 5.5 THs
(The limiting factor will remain the PSUs. The RockerBox has much more potential for over clocking)
This will be done without mask fix, just production tuning.

jtoomim more or less got it right.

Guy

My point is that TSMC will not have 'accidentally' botched 3 separate batches of lots (August, September, October). Remember, these are the same 28nm lines that Qualcomm and Broadcomm use. The notion that it is TSMC's 'fault' is simply a convenient excuse to a design mistake. I have no doubt that TSMC is capable of a retarget of your LVT devices to meet your original performance target. However, that 10% increase you were hoping to achieve with a post engineering run retarget has disappeared. Guy, I applaud your ability to perform damage control.

jtoomim, yes my name is intentionally chosen to troll. That doesn't delegitimize my arguments. Source: I run fab sync for a major US semiconductor company. You don't have to believe me, but you can do your own research on the topic.

How do you know that they didnt get all the SP30 chips in one batch? And it just takes this long to build and ship them. Plus I think its just August and September, the October batch is purported to be back up to 5.5TH so is probably separate. Thats the way I read it anyway.

I don't think TSMC makes too many mistakes, they are not worth 106 Billion dollars for nothing.

I don't know whether the mistake was in manufacturing or in design, all I meant was that it appeared to me that the concept of them making 3 batches with the same error would, as you say, not make sense. Either from SPtech's POV or TSMC. So I was suggesting that the erroneous batch was a single batch for Aug/Sep production, hence why it is being corrected in the October/Nov batch of chips from TSMC.

So say it was a production error, its only one mistake, not 3, not "too many" just one. Of course it might not have been TSMC's fault at all, but again thats not what I was talking about.